Michael Garland

See Also

Implementing sparse matrix-vector multiplication on throughput-oriented processors

Publication

N. Bell and M. Garland. Implementing sparse matrix-vector multiplication on throughput-oriented processors. Proc. SC09, November 2009.

Abstract

Sparse matrix-vector multiplication (SpMV) is of singular importance in sparse linear algebra. In contrast to the uniform regularity of dense linear algebra, sparse operations encounter a broad spectrum of matrices ranging from the regular to the highly irregular. Harnessing the tremendous potential of throughput-oriented processors for sparse operations requires that we expose substantial fine-grained parallelism and impose sufficient regularity on execution paths and memory access patterns. We explore SpMV methods that are well-suited to throughput-oriented architectures like the GPU and which exploit several common sparsity classes. The techniques we propose are efficient, successfully utilizing large percentages of peak bandwidth. Furthermore, they deliver excellent total throughput, averaging 16 GFLOP/s and 10 GFLOP/s in double precision for structured grid and unstructured mesh matrices, respectively, on a GeForce GTX 280. This is roughly 2.5 times the throughput previously achieved on Cell BE and more than 10 times that of a quad-core Intel Clovertown system.

Citation

@inproceedings{Bell2009:spmv,
    author = {Nathan Bell and Michael Garland},
    title = {Implementing sparse matrix-vector multiplication on throughput-oriented processors},
    booktitle = {SC '09: Proc. Conference on High Performance Computing Networking, Storage and Analysis},
    month = nov,
    year = 2009,
    doi = {http://doi.acm.org/10.1145/1654059.1654078},
}