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Author

Michael Garland

I am currently a research scientist with NVIDIA Research and an adjunct professor in the Department of Computer Science at the University of Illinois, Urbana-Champaign. I graduated with my Ph.D. from the Computer Science Department of Carnegie Mellon University.

My current research interests are primarily in the field of parallel programming. I also work in the areas of computer graphics and visualization.

Starting Points

• List of publications, with PDFs, movies, etc.
• Outline of research topics
• Software I’ve written

Recent Publications

• N. Bell and M. Garland. Implementing sparse matrix-vector multiplication on throughput-oriented processors. Proc. Supercomputing 2009, To appear, November 2009.

• N. Satish, M. Harris, and M. Garland. Designing efficient sorting algorithms for manycore GPUs. Proc. 23rd IEEE Int’l Parallel & Distributed Processing Symposium, May 2009. To appear. [Preprint]

• C. Lauterbach, M. Garland, S. Sengupta, D. Luebke, and D. Manocha. Fast BVH construction on GPUs, Proc. Eurographics 2009, March 2009. To appear. [PDF] [Movie (AVI)] [Details]

• N. Bell and M. Garland. Efficient sparse matrix-vector multiplication on CUDA. NVIDIA Technical Report NVR-2008-004, December 2008. [PDF] [Online]

• S. Sengupta, M. Harris, and M. Garland. Efficient parallel scan algorithms for GPUs. NVIDIA Technical Report NVR-2008-003, December 2008 [PDF]